SH7727 Datasheet, PDF (701/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
20.2.13 Receive Control Data Register (SIRCR)
This register stores the received control data for SIOF. Setting to this register is effective when
1*** is set to FL bit of SIMDR register. This register is initialized at power on reset, software
reset, or receive reset.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits 31 to 16—Receive Data for Channel 0 (SIRC015 to SIRC00): Received data from
RXD_SIO as control channel 0 data is stored to these bits. The position of control channel 0 data
is determined by the setting of CD0A bit of SICDAR register.
This bit is effective when 1 is set to CD0E bit of SICDAR register.
Bits 15 to 0—Receive Data for Channel 1 (SIRC115 to SIRC10): Received data from
RXD_SIO as control channel 1 data is stored to these bits. The position of control channel 1 data
is determined by the setting of CD1A bit of SICDAR register.
This bit is effective when 1 is set to CD1E bit of SICDAR register.
Rev. 5.00 Dec 12, 2005 page 629 of 1034
REJ09B0254-0500