SH7727 Datasheet, PDF (743/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
21.2.9 Transmit Data FIFO Port (TDFP)
TDFP is the write only port for transmit FIFO. Transmit FIFO has 128 stages (maximum), and can
generate interrupt of the data empty as well as of the threshold size specified by FFSZ (ACTR1).
Directly after the reset and when TE (ACTR1) bit is 0, the pointer of FIFO is set to the first
address and data becomes empty. The interrupt will occur when the TE bit (ACTR1) is written to
1 at that state. In normal case, TE bit should be changed after writing data into transmit FIFO.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDFP
Initial value: ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
R/W: W W W W W W W W W W W W W W W W
21.2.10 Receive Data FIFO Port (RDFP)
RDFP is the read only register for receive FIFO. Receive FIFO has 128 stages (maximum), and
can generate interrupt of the data full as well as of the threshold size specified by FFSZ (ACTR1).
Directly after the reset and when RE bit (ACTR1) is 0, the pointer of FIFO is fixed at the first
address and data from RDFP becomes undetermined.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDFP
Initial value: ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
R/W: R R R R R R R R R R R R R R R R
21.3 Operation
21.3.1 Interrupt Timing
AFE interface module generates 3 types of interrupt: FIFO data transfer, ringing detect, and dial
pulse transmit end. The timing of each interruption is described below.
(1) FIFO Interrupt Timing
Figure 21.2 shows interrupt timing of data transfer FIFO. Transmit FIFO generates the TFE and
THE interrupts after the last data is transfer red shift register. Receive FIFO generates the RFF and
RHF interrupt after the last data or specified word is transferred from shift register to FIFO.
Rev. 5.00 Dec 12, 2005 page 671 of 1034
REJ09B0254-0500