SH7727 Datasheet, PDF (712/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
Table 20.10 Receive Request Submit Condition
RFWM2 to RFWM0
000
100
101
110
111
Request Stage
Number
1
4
8
12
16
Receive Request Submit
Over 1 stage effective area
Over 4 stages effective area
Over 8 stages effective area
Over 12 stages effective area
16 stages effective area
Used Area
Small
Large
When the data area or empty area exceed the above stage number, FIFO capacity always can be
used 16 stages. Therefore, over flow or under flow error are submitted when the data area, or
empty area excesses 16 stages.
Even if FIFO is not empty or full, the transmit request is cancelled when the above conditions
become not to be satisfied.
(3) Showing of Stage Number
The state of using transmit or receive FIFO is displayed in the following registers.
• Transmit FIFO: Shows stage number of empty area to bits TFUA4 to TFUA0 in SIFCTR
register
• Receive FIFO: Shows stage number of effective data to bits RFUA4 to RFUA0 of SIFCTR
register
The above contents show the number of data which CPU or DMAC can transfer.
Rev. 5.00 Dec 12, 2005 page 640 of 1034
REJ09B0254-0500