SH7727 Datasheet, PDF (359/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Pin Name
Data enable 3
Read
Wait
Clock enable
IOIS16
Bus release request
Bus release
acknowledgment
Mode selection
Signal
WE3/DQMUU/
ICIOWR
I/O
Output
RD
WAIT
CKE
IOIS16
BREQ
Output
Input
Output
Input
Input
Section 12 Bus State Controller (BSC)
Description
When memory other than synchronous
DRAM and PCMCIA is used, selects D31
to D24 write strobe signal. When
synchronous DRAM is used, selects D31 to
D24. When PCMCIA is used, strobe signal
indicating I/O write.
Strobe signal indicating read cycle
Wait state request signal
Clock enable control signal of synchronous
DRAM
Signal indicating PCMCIA 16-bit I/O. Valid
only in little-endian mode.
Bus release request signal
BACK
MD5 to MD3
Output Bus release acknowledge signal
Input
Specifies bus width and endian of area 0
12.1.4 Register Configuration
The BSC has 11 registers (table 12.2). The synchronous DRAM also has a built-in synchronous
DRAM mode register. These registers control direct connection interfaces to memory, wait states,
and refreshes.
Rev. 5.00 Dec 12, 2005 page 287 of 1034
REJ09B0254-0500