SH7727 Datasheet, PDF (622/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 18 Smart Card Interface
With no parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitting station output
With parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Transmitting station output
Ds: Start bit
D0 to D7: Data bits
Dp: Parity bit
DE: Error signal
Receiving
station output
Figure 18.3 Data Format for Smart Card Interface
The operating sequence is:
1. The data line is high impedance when not in use and is fixed high with a pull-up resistor.
2. The transmitting side starts one frame of data transmission. The data frame starts with a start
bit (Ds, low level). The start bit is followed by eight data bits (D0 to D7) and a parity bit (Dp).
3. On the smart card interface, the data line returns to high impedance after this. The data line is
pulled high with a pull-up resistor.
4. The receiving side checks parity. When the data is received normally with no parity errors, the
receiving side then waits to receive the next data. When a parity error occurs, the receiving
side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving
station returns the signal line to high impedance after outputting the error signal for a specified
period. The signal line is pulled high with a pull-up resistor.
5. The transmitting side transmits the next frame of data unless it receives an error signal. If it
does receive an error signal, it returns to step 2 to re-transmit the erroneous data.
Rev. 5.00 Dec 12, 2005 page 550 of 1034
REJ09B0254-0500