SH7727 Datasheet, PDF (284/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
8.2.7 Break Data Mask Register B (BDMRB)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified
by BDRB. A power-on reset initializes BDMRB to H'00000000.
XYE = 0
XYE = 1
BDMB31 to 16
Mask L(I) DB31 to 16
Mask XDB15 to 0 (XYS = 0)
BDMB15 to 0
Mask L(I) DB15 to 0
Mask YDB15 to 0 (XYS = 1)
Bits 31 to 0:
BDMBn
Description
0
Break data BDBn of channel B is included in the break condition (Initial value)
1
Break data BDBn of channel B is masked and is not included in the break
condition
n = 31 to 0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When a byte size is selected as a break condition, the same break data (byte size)
must be set both in bits 15 to 8 and in bits 7 to 0 in BDRB.
Rev. 5.00 Dec 12, 2005 page 212 of 1034
REJ09B0254-0500