SH7727 Datasheet, PDF (71/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 27.8 Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 856
Section 28 A/D Converter
Table 28.1 A/D Converter Pins.................................................................................................. 859
Table 28.2 A/D Converter Registers ........................................................................................ 860
Table 28.3 Analog Input Channels and A/D Data Registers .................................................... 861
Table 28.4 A/D Conversion Time (Single Mode) .................................................................... 874
Table 28.5 Analog Input Pin Ratings ....................................................................................... 878
Table 28.6 Relationship between Access Size and Read Data ................................................. 878
Section 29 D/A Converter
Table 29.1 D/A Converter Pins ................................................................................................ 880
Table 29.2 D/A Converter Registers ........................................................................................ 880
Section 30 PC Card Controller (PCC)
Table 30.1 PC Card Controller Registers ................................................................................. 887
Table 30.2 Features of the PCMCIA Interface......................................................................... 888
Table 30.3 PCMCIA Support Interface.................................................................................... 904
Section 31 User-Debugging Interface (H-UDI)
Table 31.1 H-UDI Registers..................................................................................................... 917
Table 31.2 H-UDI Commands ................................................................................................. 918
Table 31.3 Correspondence between SH7727 Pins and Boundary-Scan Register ................... 919
Table 31.4 Reset Configuration................................................................................................ 926
Section 32 Electrical Characteristics
Table 32.1 Absolute Maximum Ratings................................................................................... 929
Table 32.2 DC Characteristics (1) ............................................................................................ 931
Table 32.2 DC Characteristics (2) ............................................................................................ 933
Table 32.3 Permitted Output Current Values ........................................................................... 934
Table 32.4 Maximum Operating Frequencies (1) .................................................................... 936
Table 32.4 Maximum Operating Frequencies (2) .................................................................... 936
Table 32.5 Clock Timing (1) .................................................................................................... 937
Table 32.6 Clock Timing (2) .................................................................................................... 938
Table 32.7 Clock Timing (3) .................................................................................................... 939
Table 32.8 Clock Timing (4) .................................................................................................... 940
Table 32.9 Control Signal Timing............................................................................................ 946
Table 32.10 Bus Timing............................................................................................................. 949
Table 32.11 Peripheral Module Signal Timing .......................................................................... 975
Table 32.12 H-UDI-Related Pin Timing .................................................................................... 978
Table 32.13 LCDC Timing ........................................................................................................ 980
Rev. 5.00 Dec 12, 2005 page lxxi of lxxii