SH7727 Datasheet, PDF (486/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0
CSn
D31 to D0
RD
WEn
Transfer
+4
source address
DACKn
+8
+12
Figure 14.13 Example of DMA Transfer Timing in Single Address Mode
(External Memory Space (Ordinary Memory) → External Device with DACK)
Bus Modes: There are two types of bus modes, cycle steal mode and burst mode. Select the mode
in the TM bits in CHCR0 to CHCR3.
• Cycle-Steal Mode
In the cycle-steal mode, the bus right is moved to another bus master after one transfer unit (byte,
word, longword, or 16-byte unit) of DMA transfer. If another transfer request occurs after the bus
right moving, the bus right are re-moved to the DMAC. Then, the DMAC performs transfer for
one transfer unit and releases the bus right again. This operation is repeated until the transfer end
condition is satisfied.
In the cycle-steal mode, transfer areas are not affected by settings of the transfer request source,
transfer source, and transfer destination. Figure 14.14 shows an example of the DMA transfer
timing in the cycle steal mode. In this example, the following conditions are set:
• Dual address mode
• DREQ level detection
Rev. 5.00 Dec 12, 2005 page 414 of 1034
REJ09B0254-0500