SH7727 Datasheet, PDF (444/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Li Bus State Controller (LBSC)
13.1.6 Wait State Control Register 2 (WCR2)
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in
standby mode.
Bit:
Initial value:
R/W:
15
A6W2
1
R/W
14
A6W1
1
R/W
13
A6W0
1
R/W
12
A5W2
1
R/W
11
A5W1
1
R/W
10
A5W0
1
R/W
9
A4W2
1
R/W
8
A4W1
1
R/W
Bit:
Initial value:
R/W:
7
A4W0
1
R/W
6
A3W1
1
R/W
5
A3W0
1
R/W
4
A2W1
1
R/W
3
A2W0
1
R/W
2
A0W2
1
R/W
1
A0W1
1
R/W
0
A0W0
1
R/W
Bits 15 to 7 and 4 to 0 —Not referenced
Bits 6 and 5— Area 3 Wait Control (A3W1, A3W0): Specifies the CAS latency for the
SDRAM of area 3 of the physical space.
Bit 6: A3W1
0
1
Bit 5: A3W0
0
1
0
1
Description
SDRAM CAS Latency
1
1
2
3
(Initial value)
Rev. 5.00 Dec 12, 2005 page 372 of 1034
REJ09B0254-0500