SH7727 Datasheet, PDF (660/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.10 FIFO Data Count Set Register 2 (SCFDR2)
The SCFDR2 is a 16-bit register which indicates the number of data stored in the transmit FIFO
data register 2 (SCFTDR2) and the receive FIFO data register 2 (SCFRDR2). It indicates the
number of transmit data in the SCFTDR2 with the upper eight bits, and the number of receive data
in the SCFRDR2 with the lower eight bits. The SCFDR2 is always read from the CPU.
Upper 8 Bits: 15
14
13
12
11
10
9
8
—
—
—
T4
T3
T2
T1
T0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The SCFDR2 indicates the number of non-transmitted data stored in the SCFTDR2. The H'00
means no transmit data, and the H'10 means that the full of transmit data are stored in the
SCFTDR2.
Lower 8 Bits: 7
6
5
4
3
2
1
0
—
—
—
R4
R3
R2
R1
R0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The SCFDR2 indicates the number of receive data stored in the SCFRDR2. The H'00 means no
receive data, and the H'10 means that the full of receive data are stored in the SCFRDR2.
Rev. 5.00 Dec 12, 2005 page 588 of 1034
REJ09B0254-0500