SH7727 Datasheet, PDF (945/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 28 A/D Converter
28.4.4 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit of ADCSR is set to 1, then starts conversion. Figure 28.6
shows the A/D conversion timing. Table 28.4 indicates the A/D conversion time.
As indicated in figure 28.6, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 28.4.
In multi mode and scan mode, the values given in table 28.4 apply to the first conversion. In the
second and subsequent conversions the conversion time is fixed at 536 states when CKS = 0 or
266 states when CKS = 1.
In all cases, the CKS bit in ADCSR should be set according to the frequency of Pφ so that the
conversion time is within the range shown in table 32.16 in section 32, Electrical Characteristics.
(1)
Pφ
Address
(2)
Write signal
Input sampling timing
ADF
t_D
t_SPL
t_CONV
(1) : ADCSR write cycle
(2) : ADCSR address
t_D : A/D conversion start delay
t_SPL : Input sampling time
t_CONV : A/D conversion time
Figure 28.6 A/D Conversion Timing
Rev. 5.00 Dec 12, 2005 page 873 of 1034
REJ09B0254-0500