SH7727 Datasheet, PDF (441/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Li Bus State Controller (LBSC)
Bits 4 to 2—Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Specifies
the type of memory connected to the physical space areas 2 and 3. Before using LCDC and USB,
set area 3 to synchronous DRAM (DRAMTP2 to DRAMTP0 equal to 010 or 011).
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
0
0
Ordinary memory for areas 2 and 3
(Initial value)
1
Reserved (Setting disabled)
1
0
Ordinary memory for area 2 and
synchronous DRAM for area 3^*1
1
Synchronous DRAM for areas 2 and 3^{*1 *2}
1
0
0
Reserved
1
Reserved
1
0
Reserved (Setting disabled)
1
Reserved (Setting disabled)
Notes: 1. It is not possible to access synchronous DRAM if clock ratio Iφ:bus clock = 1:1.
2. When selecting this mode, set the same bus width for area 2 and area 3.
Bits 1 and 0 —Not referenced
Rev. 5.00 Dec 12, 2005 page 369 of 1034
REJ09B0254-0500