SH7727 Datasheet, PDF (744/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
AFE_FS
AFE_TX
OUT
Data 1
Data 2
Half−1
Half
TFE/TTE
AFE_FS
AFE_RX
First
First+1
Half−1
Half
IN
RFF/RTF
Figure 21.2 FIFO Interrupt Timing
(2) Ringing Interrupt Timing
As the figure 21.3 shows, the ringing signal from the line is transformed to rectangular wave and
then input to AFEIF. The interrupt is generated at the rising edge of input wave in AFEIF module.
Ringing wave
Input wave
INT. occur
Figure 21.3 Ringing Interrupt Occurrence Timing
(3) Dial Pulse Interrupt Timing
Dial pulse interrupt is generated in the dial pulse transmit sequence when AFEIF reads 0H (end)
data from DPNQ register or all of 4 digits are output. Refer to section 21.3.3, DAA Interface about
dial pulse sequence.
Rev. 5.00 Dec 12, 2005 page 672 of 1034
REJ09B0254-0500