SH7727 Datasheet, PDF (787/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 23 USB Function Controller
EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit-data writes
without being aware of this dual-FIFO configuration. Write data to one FIFO at one time. For
instance, even if two FIFOs are empty, EP2/PKTE cannot be performed after writing 128-byte
data continuously. Perform EP2/PKTE in every 64-byte write.
To perform bulk-in transfer, since there is no valid data in FIFO in the first in-token, a
USBIFR0/EP2 TR interrupt is requested. By the interrupt, write 1 to the USBIER0/EP2 EMPTY
bit and enable the EP2 FIFO EMPTY interrupt. Since the two EP2 FIFOs are empty first, the EP2
FIFO EMPTY interrupt is generated immediately.
The data to be transmitted is written to the data register using this interrupt. After the first
transmit data write, the other FIFO is empty, and so the next transmit data can be written
immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one FIFO is
empty, USBIFR0/EP2 EMPTY is set to 1. When ACK is returned from the host after data
transmission is completed, the FIFO used in the data transmission becomes empty. If the other
FIFO contains valid transmit data at this time, transmission is continued.
When transmission of all data has been completed, write 0 to USBIFR0/EP2 EMPTY and disable
interrupt requests.
Rev. 5.00 Dec 12, 2005 page 715 of 1034
REJ09B0254-0500