SH7727 Datasheet, PDF (452/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
 Channel 3: Can accept requests from peripheral modules. Direct address transfer mode or
indirect address transfer mode can be specified.
• Reload function: The value that was specified in the source address register can be
automatically reloaded every 4 DMA transfers. This function is only valid in channel 2.
• Three types of transfer requests
 External requests (From two DREQ pins (channels 0 only). DREQ can be detected either
by falling edge or by low level)
 On-chip module requests (Requests from on-chip supporting modules such as serial
communications interface (SIOF, SCIF), A/D converter (A/D) and a timer (CMT) . This
request can be accepted in all the channels)
 Auto requests (the transfer request is generated automatically within the DMAC)
• Selectable bus modes: Cycle-steal mode or burst mode
• Selectable channel priority levels:
Fixed mode: The channel priority is fixed.
Round-robin mode: The priority of the channel in which the execution request was accepted is
made the lowest.
• Interrupt request: An interrupt request can be generated to the CPU after the specified number
of times of transfers.
Rev. 5.00 Dec 12, 2005 page 380 of 1034
REJ09B0254-0500