SH7727 Datasheet, PDF (840/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
Bits 4 to 0—Denominator of Clock Division Ratio (DCDR4 to DCDR0): Set denominator of
the input clock division ratio.
I/O Clock Frequency (MHz)
DCDR[4:0]
Clock Division Ratio
50.000
00001
1/1
50.000
(Initial value)
00010
1/2
25.000
00100
1/4
12.500
01000
1/8
6.250
10000
1/16
3.125
Any setting other than above is handled as a clock division ratio of 1/1 (initial value).
Note: The access size indicates the size the CPU uses to access (read from or write to) the
register. When accessing this register in a size other than the displayed one, LCDC
operation is not guaranteed.
Only 0 can be written to a reserved bit.
When a setting not allowed is made, e.g. a reserved bit is written to, though the LCDC
operates with its initial values, normal operation is not guaranteed.
This is the common rule to all registers in this LCDC.
25.2.2 LCDC Module Type Register (LDMTR)
LDMTR sets the control signals output from this LCDC and the polarity of the data signals,
according to the polarity of the signals for the LCD module connected to the LCDC.
Bit: 15
14
13
12
11
10
9
8
7
FLM CL1 DISP DPOL — MCNT CL1 CL2 —
POL POL POL
CNT CNT
Initial value: 0
0
0
0
0
0
0
1
0
R/W: R/W R/W R/W R/W
R
R/W R/W R/W
R
6
5
4
3
2
1
0
— MIF MIF MIF MIF MIF MIF
TYP5 TYP4 TYP3 TYP2 TYP1 TYP0
0
0
0
1
0
0
1
R R/W R/W R/W R/W R/W R/W
Bits 11, 7, and 6—Reserved
Bit 15—FLM (Vertical Sync Signal) Polarity Select (FLMPOL): Selects the polarity of the
FLM (vertical sync signal, first line marker) for the LCD module.
Bit 15
FLMPOL
0
1
Description
FLM pulse is high active
FLM pulse is low active
(Initial value)
Rev. 5.00 Dec 12, 2005 page 768 of 1034
REJ09B0254-0500