SH7727 Datasheet, PDF (857/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
Bit 12—Vsync Interrupt Select (VINTSEL): Sets the starting point of the LCDC’s Vsync
interrupt.
Bit 12
VINTSEL
0
1
Description
Vsync interrupt is generated at starting point of vertical retrace period for memory
access
(Initial value)
Vsync interrupt is generated at starting point of vertical retrace period for LCD display
Bit 8—Vsync Interrupt Enable (VINTE): Sets whether or not to enable LCDC’s Vsync
interrupts.
Bit 8
VINTE
0
1
Description
Vsync interrupts are disabled
Vsync interrupts are enabled
(Initial value)
Bit 0—Vsync Interrupt State (VINTS): Indicates the LCDC’s Vsync interrupt handling state.
This bit is set to 1 at the time a Vsync interrupt is generated. During the Vsync interrupt handling
routine, this bit should be cleared by writing 0 to it.
Bit 0
VINTS
0
1
Description
LCDC did not generate a Vsync interrupt or has been informed that the generated
Vsync interrupt has completed
(Initial value)
LCDC has generated a Vsync interrupt and has not yet been informed that the
generated Vsync interrupt has completed
Notes: •
•
Interrupt Handling Flow:
1. An interrupt signal is input to the CPU.
2. The CPU reads from VINTS.
3. If VINTS is set to 1, a Vsync interrupt has occurred, and the Vsync interrupt
handling is carried out.
4. If VINTS is cleared to 0, no Vsync interrupt has occurred and another processing is
carried out.
When Vsync interrupts are enabled, the VINTE bit must be set to 1 before the DON bit
is set to 1, and the VINTE bit must not be cleared to 0.
Rev. 5.00 Dec 12, 2005 page 785 of 1034
REJ09B0254-0500