SH7727 Datasheet, PDF (251/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.3 INTC Registers
Section 7 Interrupt Controller (INTC)
7.3.1 Interrupt Priority Registers A to G (IPRA to IPRG)
Interrupt priority registers A to G (IPRA to IPRG) are 16-bit read/write registers that set priority
levels from 0 to 15 for on-chip supporting module, IRQ, and PINT interrupts. These registers are
initialized to H'0000 at power-on reset, and manual reset, but are not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 7.7 lists the relationship between the interrupt sources and the IPRA to IPRG bits.
Table 7.7 Interrupt Request Sources and IPRA to IPRG
Register
Bits 15 to 12
Bits 11 to 8
IPRA
TMU0
TMU1
IPRB
WDT
REF
IPRC
IRQ3
IRQ2
IPRD
PINT0 to PINT7 PINT8 to PINT15
IPRE
DMAC
Reserved*
IPRF
Reserved*
LCDC
IPRG
USBH
USBF0
Note: * Always read as 0. Only 0 should be written in.
Bits 7 to 4
TMU2
SCI
IRQ1
IRQ5
SCIF
PCC0
USBF1
Bits 3 to 0
RTC
Reserved*
IRQ0
IRQ4
ADC
SIOF
AFEIF
As listed in table 7.7, four sets of on-chip supporting modules or IRQ or PINT interrupts are
assigned to each register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set
with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is
requested); H'F is priority level 15 (the highest level). A reset initializes IPRA to IPRG to H'0000.
Rev. 5.00 Dec 12, 2005 page 179 of 1034
REJ09B0254-0500