SH7727 Datasheet, PDF (267/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
Bit 5—USBF1I Interrupt Request (USBF1IR): Indicates whether a USBF1I (USB function)
interrupt request is generated.
Bit 5: USBF1IR
0
1
Description
A USBF1I interrupt request is not generated
A USBF1I interrupt request is generated
(Initial value)
Bit 4—AFEIFI Interrupt Request (AFEIFIR): Indicates whether a AFEIFI (AFE I/F) interrupt
request is generated.
Bit 4: AFEIFIR
0
1
Description
An AFE I/F interrupt request is not generated
An AFE I/F interrupt request is generated
(Initial value)
Bits 3 to 0—Reserved: These bits are always read as 0.
7.3.11 Interrupt Request Register 4 (IRR4)
The IRR4 is a 16-bit read-only register that indicates whether SIOF interrupt requests are
generated. This register is initialized to H'0000 at power-on reset or manual reset, but is not
initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
ERI
TXI
RXI
CCI
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 5.00 Dec 12, 2005 page 195 of 1034
REJ09B0254-0500