SH7727 Datasheet, PDF (606/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Serial Data Reception (Clock Synchronous Mode):
Figure 17.21 shows a sample flow chart for serial data reception. After enabling the SCI
transmission, transmit serial data following the procedure shown below:
When switching from the asynchronous mode to the clock synchronous mode, make sure that
ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and
both transmitting and receiving will be disabled.
Start reception
Read ORER bit in SCSSR
ORER = 1?
No
Yes
(1)
Error processing
Read RDRF bit in SCSSR
(2)
No
RDRF = 1?
Yes
Read receive data in SCRDR and
clear RDRF bit in SCSSR to 0 ⁽³⁾
No
All data received?
Yes
Clear RE bit in SCSCR to 0
(1) Receive error processing:
If a receive error occurs, read
the ORER bit in SCSSR to
identify the error. After
executing the necessary error
processing, clear ORER to 0.
Transmitting/receiving cannot
resume if ORER remains set
to 1.
(2) SCI status check and receive
data read:
Read the serial status register
(SCSSR), check that RDRF is
set to 1, then read receive
data from the receive data
register (SCRDR) and clear
RDRF to 0. The RXI interrupt
can also be used to determine
if the RDRF bit has changed
from 0 to 1.
(3) To continue receiving serial
data:
Read SCRDR, and clear
RDRF to 0 before the frame
MSB (bit 7) of the current
frame is received.
End reception
Figure 17.21 Sample Serial Reception Flowchart (1)
Rev. 5.00 Dec 12, 2005 page 534 of 1034
REJ09B0254-0500