SH7727 Datasheet, PDF (320/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Power-Down Modes and Software Reset
Bit
Value Description
MSTP17 0
SIOF runs.
1
Clock supply to SIOF halted.
MSTP15 0
AFEIF runs.
1
Clock supply to AFEIF halted.
MSTP14 0
USBF runs.
1
Clock supply to USBF halted.
MSTP13 0
USBH runs.
1
Clock supply to USBH halted.
This bit should not be set to 1 when MSTP14 (bit 4) is 0.
MSTP11 0
LCDC runs.
1
Clock supply to LCDC halted.
MSTP10 0
PCC runs.
1
Clock supply to PCC halted.
MSTP9 0
X/Y memory runs.
1
Clock supply to X/Y memory halted.
MSTP8 0
UBC runs.
1
Clock supply to UBC halted.
MSTP7 0
DMAC runs.
1
Clock supply to DMAC halted.
MSTP6 0
DAC runs.
1
Clock supply to DAC halted.
MSTP5 0
ADC runs.
1
Clock supply to ADC halted, and all registers initialized.
MSTP4 0
SCIF runs.
1
Clock supply to SCIF halted.
MSTP2 0
1
TMU runs.
Clock supply to TMU halted.^*1
MSTP1 0
1
RTC runs.
Clock supply to RTC halted. Register access prohibited.^*2
MSTP0 0
SCI runs.
1
Clock supply to SCI halted.
Notes: 1. The initialized registers are the same as in the standby mode (see table 9.4).
2. The counter runs.
Rev. 5.00 Dec 12, 2005 page 248 of 1034
REJ09B0254-0500