SH7727 Datasheet, PDF (459/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3)
Bit: 31
...
21
20
19
18
17
16
—
...
—
DI
RO
RL
AM
AL
Initial value: 0
...
0
0
0
0
0
0
R/W: R
...
R
(R/W)^*2 (R/W)^*2 (R/W)^*2 (R/W)^*2 (R/W)^*2
Bit: 15
14
13
12
11
10
9
8
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
—
DS
TM
TS1
TS0
IE
TE
DE
Initial value: 0
0
0
0
0
0
0
0
R/W:
R
(R/W)^*2 R/W
R/W
R/W
R/W R/(W)^*1 R/W
Notes: 1. Only a write of 0 after a read of 1 is enabled for the TE bit.
2. DI, RO, RL, AM, AL, and DS bits are not included in some channels.
The DMA channel control registers 0 to 3 (CHCR0 to CHCR3) are 32-bit read/write registers that
specify operation mode, transfer method, or others in each channel. Writing to bits 31 to 21 and 7
in this register is invalid, and these bits are always read as 0.
Bit 20 is only used in CHCR3. It is not used in CHCR0 to CHCR2. Consequently, writing to this
bit is invalid in CHCR0 to CHCR2, and this bit is always read as 0.
Bit 19 is only used in CHCR2. It is not used in CHCR0, CHCR1, and CHCR3. Consequently,
writing to this bit is invalid in CHCR0, CHCR1, and CHCR3, and this bit is always read as 0.
Bits 6 and 16 to 18 are only used in CHCR0 and CHCR1. They are not used in CHCR2 and
CHCR3. Consequently, writing to these bits is invalid in CHCR2 and CHCR3, and these bits are
always read as 0.
These registers are initialized to 0 after a power-on reset. The previous values are held in standby
mode.
Bits 31 to 21—Reserved: These bits are always read as 0 and should only be written with 0.
Rev. 5.00 Dec 12, 2005 page 387 of 1034
REJ09B0254-0500