SH7727 Datasheet, PDF (270/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
Program
execution state
Yes
ICR1.MAI = 1?
No _No
Interrupt
generated?
NMI = low?
Yes
No
No
ICR1.BLMSK = 1?
Yes
NMI?
No
Yes
Yes
Yes
No
SR.BL= 0
or sleep mode?
Yes
NMI?
No
Level 15
No
interrupt?
Set interrupt cause in
INTEVT, INTEVT2
Save SR to SSR;
save PC to SPC
Set BL/MD/RB
bits in SR to 1
Yes
Level 14
No
interrupt?
Yes
I3−I0 level
14 or lower?
Yes
Level 1
No
interrupt?
No
Yes
I3−I0 level
13 or lower?
Yes
No
Yes
I3−I0
level 0?
No
Branch to exception
handler
I3−I0: Interrupt mask bits in status register (SR)
Figure 7.3 Interrupt Operation Flowchart
Rev. 5.00 Dec 12, 2005 page 198 of 1034
REJ09B0254-0500