SH7727 Datasheet, PDF (935/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 28 A/D Converter
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5: ADST
0
1
Description
A/D conversion is stopped
(Initial value)
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends.
Multi mode: A/D conversion starts, cycling among the selected channels. After the
cycling has been completed, ADST is cleared to 0.
Scan mode: A/D conversion starts and continues, until ADST is cleared to 0 by
software, by a reset, or by a transition to standby mode.
Bit 4—Multi Mode (MULTI): Selects single mode, multi mode or scan mode. For further
information on operation in these modes, see section 28.4, Operation.
Bit 4: MULTI
0
1
ADCR:
Bit 5: SCN
0
1
0
1
Description
Single mode
Multi mode
scan mode
(Initial value)
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3:CKS
Description
0
Conversion time = 536 states (maximum)
1
Conversion time = 266 states (maximum)^*
(Initial value)
Note: * The CKS value should be set so that the A/D conversion time is 16 µs (minimum).
Rev. 5.00 Dec 12, 2005 page 863 of 1034
REJ09B0254-0500