SH7727 Datasheet, PDF (786/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 23 USB Function Controller
and so the next packet can be received immediately. When both FIFOs are full, NACK is returned
to the host automatically. When reading of the receive data is completed following data reception,
1 is written to the USBTRG/EP1 RDFN bit. This operation empties the FIFO that has just been
read, and makes it ready to receive the next packet.
23.6.5 EP2 Bulk-In Transfer (Dual FIFOs)
USB function
IN token reception
Application
Valid data
in EP2 FIFO?
Yes
No
NACK
Data transmission to host
ACK
USBIFR0/EP2 TR interrupt
Write 1 to USBIER0/EP2
EMPTY enable bit
Space
in EP2 FIFO?
No
USBIFR0/EP2 ^Interrupt
Yes _{EMPTY status} request
bit automatically
set 1
USBIFR0/EP2 EMPTY status
bit automatically cleared to 0
USBIFR0/EP2 EMPTY
interrupt
Write one-packet data to
USBEP2 data register
Write 1 to EP2 packet
enable bit
(USBTRG/EP2 PKTE = 1)
Figure 23.11 EP2 Bulk-In Transfer Operation
Rev. 5.00 Dec 12, 2005 page 714 of 1034
REJ09B0254-0500