SH7727 Datasheet, PDF (801/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 24 USB HOST Module
24.2.2 HcControl
HcControl Register (H'04000404)
The HcControl register defines the operation mode for the host controller. Most of bits of this
register are amended only by the host controller driver other than HostController Function State
and Remote Wakeup Command.
Register: HcControl
Bits
Reset R/W
31–11 0h
—
10
0b
R/W
9
0b
R/W
8
0b
R/W
Offset: 04–07
Description
Reserved. Read/Write 0's
RemoteWakeupEnable (RWE)
This bit is used by HCD to enable/disable the remote wakeup
function at the same time as the detection of an upstream
resume signal. This function is not supported. Be sure to write
0.
RemoteWakeupConnected (RWC)
This bit indicates whether the host controller supports a remote
wakeup signal or not. When the remote wakeup is supported
and used in the system, the host controller must set this bit
between POST in the system firmware. The host controller
clears the bit at the same time of the hardware reset, however,
does not change at the same time as the software reset. The
remote wakeup signal to the system of the host is specific for
the host bus, so it is not described in this specification.
0: Remote wakeup signal is not supported. (initial value)
1: Remote wakeup signal is supported.
InterruptRouting (IR)
This bit determines the routing of interrupts generated by the
event registered in HcInterruptStatus. HCD clears this bit at the
same time as the hardware reset, however, does not clear at
the same time as the software reset. HCD uses this bit as a tag
to indicate the ownership of the host controller.
0: All interrupts are routed to normal bus interrupt mechanism.
(initial value)
1: Interrupts are routed to SMI.
Rev. 5.00 Dec 12, 2005 page 729 of 1034
REJ09B0254-0500