SH7727 Datasheet, PDF (249/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
(Initial IPR (Bit
Value) Numbers)
Priority
within IPR
Setting Default
Unit
Priority
ADC ADI
H'200–3C0* (H'980) 0–15 (0) IPRE (3–0) —
High
LCDC LCDCI
H'200–3C0* (H'9A0) 0–15 (0) IPRF (11–8) —
SIOF SIFERI
H'200–3C0* (H'B00) 0–15 (0) IPRF (3–0) High
SIFTXI
H'200–3C0* (H'B20) 0–15 (0)
SIFRXI
H'200–3C0* (H'B40) 0–15 (0)
SIFCCI
H'200–3C0* (H'B60) 0–15 (0)
Low
USBH USBHI
H'200–3C0* (H'A00) 0–15 (0) IPRG (15–12) —
USBF USBFI0
H'200–3C0* (H'A20) 0–15 (0) IPRG (11–8) High
USBFI1
H'200–3C0* (H'A40) 0–15 (0) IPRG (7–4) Low
AFEIF AFEIFI
H'200–3C0* (H'A60) 0–15 (0) IPRG (3–0) —
PCC0 PC0SWIR
H'200–3C0* (H'9C0) 0–15 (0) IPRF (7–4) High
PC0IRIR
H'200–3C0* (H'9C0) 0–15 (0)
PC0SCIR
H'200–3C0* (H'9C0) 0–15 (0)
PC0CDIR
H'200–3C0* (H'9C0) 0–15 (0)
PC0RCIR
H'200–3C0* (H'9C0) 0–15 (0)
PC0BWIR
H'200–3C0* (H'9C0) 0–15 (0)
PC0BDIR
H'200–3C0* (H'9C0) 0–15 (0)
Low
TMU0 TUNI0
H'400 (H'400)
0–15 (0) IPRA (15–12) —
TMU1 TUNI1
H'420 (H'420)
0–15 (0) IPRA (11–8) —
TMU2 TUNI2
H'440 (H'440)
0–15 (0) IPRA (7–4) —
RTC ATI
H'480 (H'480)
0–15 (0) IPRA (3–0) High
PRI
H'4A0 (H'4A0)
CUI
H'4C0 (H'4C0)
Low
SCI0 ERI
H'4E0 (H'4E0)
0–15 (0) IPRB (7–4) High
RXI
H'500 (H'500)
TXI
H'520 (H'520)
TEI
H'540 (H'540)
Low
WDT ITI
H'560 (H'560)
0–15 (0) IPRB (15–12) —
REF RCMI
H'580 (H'580)
0–15 (0) IPRB (11–8) High
ROVI
H'5A0 (H'5A0)
Low
Low
Note: * The code corresponding to an interrupt level shown in table 7.6 is set.
Rev. 5.00 Dec 12, 2005 page 177 of 1034
REJ09B0254-0500