SH7727 Datasheet, PDF (430/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
I/O Card Interface Timing: Figures 12.30 and 12.31 show the timing for the PCMCIA I/O card
interface.
Switching between the I/O card interface and the IC memory card interface is performed
according to the accessed address. When PCMCIA is designed for physical space area 5, the bus
access is automatically performed as an I/O card interface access when a physical address from
H'16000000 to H'17FFFFFF is accessed. When PCMCIA is designated for physical space area 6,
the bus access is automatically performed as an I/O card interface access when a physical address
from H'1A000000 to H'1BFFFFFF is accessed.
When accessing a PCMCIA I/O card, the access should be performed using a non-cacheable area
in virtual space (P2 or P3 space) or an area specified as non-cacheable by the MMU.
When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic
sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set for
area 5 or area 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is
recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the
I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits.
Figure 12.32 shows the basic timing for dynamic bus sizing.
In big-endian mode, the IOIS16 signal is not supported.
In big-endian mode, the IOIS16 signal should be fixed low.
Rev. 5.00 Dec 12, 2005 page 358 of 1034
REJ09B0254-0500