SH7727 Datasheet, PDF (105/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Table 2.2 Detail Behavior Under Each SH3-DSP Mode
Fields
Supervisor
Mode
MD = 1 &
DSP = 0
User Mode
MD = 0 &
DSP = 0
DSP
Supervisor
Mode
MD = 1 &
DSP = 1
DSP User
Mode
MD = 0 &
DSP = 1
Access to
DSP Related
Bits by
Dedicated
Instruction
MD
S: OK,
S, L: illegal
S: OK,
S: OK,
L: OK
instruction
L: OK
L: NG
RB
S: OK,
S, L: illegal
S: OK,
S: OK,
L: OK
instruction
L: OK
L: NG
BL
S: OK,
S, L: illegal
S: OK,
S: OK,
L: OK
instruction
L: OK
L: NG
RC [11:0] S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
SETRC
instruction
DSP
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
DMX
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
DMY
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
Q
S: OK,
S, L: illegal
S: OK,
S: OK,
L: OK
instruction
L: OK
L: NG
M
S: OK,
S, L: illegal
S: OK,
S: OK,
L: OK
instruction
L: OK
L: NG
I [3:0]
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
RF [1:0]
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
SETRC
instruction
S
S: OK,
S, L: illegal
S: OK,
S: OK,
L: OK
instruction
L: OK
L: NG
T
S: OK,
S, L: illegal
S: OK,
S: OK,
L: OK
instruction
L: OK
L: NG
(S) STC:
(L) LDC:
OK:
Store SR to Rn, SR → Rn
Load Rn to SR, Rn → SR
Allowed to STC/LSC operation
Illegal instruction: Treated as illegal instruction, exception should be occurred
NG:
Keep previous value, nothing changed
Initial Value after
Reset
1
1
1
0b000000000000
0
0
0
X
X
1111
X
X
X
Third one is single-data transfer instruction, “MOVS.W” and “MOVS.L”. This instruction
accesses any memory location through LDB (figure 2.8). All DSP registers connect to the LDB
and be able to be source and destination register of the data transfer. It has word and longword
access modes. In the word mode, registers to be loaded or stored by this instruction are upper 16
bits (bits 31 to 16) for the DSP registers except A0G and A1G. When data is loaded into a register
Rev. 5.00 Dec 12, 2005 page 33 of 1034
REJ09B0254-0500