SH7727 Datasheet, PDF (456/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.2 Register Descriptions
14.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3)
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
…
0
…
Initial value: —
—
—
—
…
—
R/W: R/W
R/W
R/W
R/W
…
R/W
The DMA source address registers 0 to 3 (SAR0 to SAR3) are 32-bit read/write registers that
specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the
next source address.
To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value. If any other address is specified, correct operation is not guaranteed.
Initial values are undefined after a reset. The previous values are held in standby mode.
Rev. 5.00 Dec 12, 2005 page 384 of 1034
REJ09B0254-0500