SH7727 Datasheet, PDF (595/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Transmitting and Receiving Data
Multiprocessor Serial Data Transmission:
Figure 17.13 shows a sample flow chart for multiprocessor serial data transmission. After enabling
the SCI transmission, transmit multiprocessor serial data following the procedure shown below:
Start transmission
Read TDRE bit in SCSSR
(1)
No
TDRE = 1?
Yes
Write transmission data to SCTDR
and set MPBT bit in SCSSR
Clear TDRE bit to 0
Transmission ended?
Yes
Read TEND bit in SCSSR
No ₍₂₎
TEND = 1?
No
Yes
No
Break output?
Yes ⁽³⁾
Set SCPDR and SCPCR
(1) SCI status check and transmit data
write:
Read the serial status register
(SCSSR), check that the TDRE bit is
1, then write transmit data in the
transmit data register (SCTDR). Also
set MPBT (multiprocessor bit transfer)
to 0 or 1 in SCSSR. Finally, clear
TDRE to 0.
(2) To continue transmitting serial data:
Read the TDRE bit to check whether it
is safe to write (if it reads 1); if so, write
data in SCTDR, then clear TDRE to 0.
(3) To output a break at the end of serial
transmission:
Set the port SC data register (SCPDR)
and port SC control register (SCPCR),
then clear the TE bit to 0 in the serial
control register (SCSCR). For SCPCR
and SCPDR settings, see section
17.2.8, Port SC Control Register
(SCPCR)/Port SC Data Register
(SCPDR).
Clear TE bit SCSCR to 0
End transmission
Figure 17.13 Sample Multiprocessor Serial Transmission Flowchart
Rev. 5.00 Dec 12, 2005 page 523 of 1034
REJ09B0254-0500