SH7727 Datasheet, PDF (116/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
2.4 Instruction Formats
2.4.1 CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Register
direct
Instruction
Format
Rn
Register
indirect
@Rn
Register
indirect with
post-
increment
@Rn+
Register
indirect with
pre-
decrement
@–Rn
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Calculation
Formula
—
Rn
Rn
Rn
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4 ₊
1/2/4
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn − 1/2/4 _−
Rn − 1/2/4
1/2/4
Rn
After instruction
execution
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction
executed with Rn
after calculation)
Rev. 5.00 Dec 12, 2005 page 44 of 1034
REJ09B0254-0500