SH7727 Datasheet, PDF (679/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

20.1.3 Terminal
Table 20.1 shows pin list of SIOF.
Table 20.1 SIOF Pin List
Name
Clock input pin
Communication clock pin
Symbol
I/O
SIOMCLK
I
SCK_SIO
I/O
Frame sync pin
SIOFSYNC I/O
Transmit data pin
Receive data pin
TXD_SIO
O
RXD_SIO
I
Section 20 Serial IO (SIOF)
Function
Master clock input
Serial clock (common for transmitting/
receiving)
Frame synchronized signal (common for
transmitting/receiving)
Transmit data
Receive data
20.1.4 Register Configuration
Table 20.2 lists the internal registers of SIOF.
Table 20.2 SIOF Register Configuration
Name
Initial
Symbol R/W Value Address
Access
Size
Serial mode register
SIMDR R/W H'0000 H'040000C0 (H'A40000C0)* 16
Clock select register
SISCR R/W H'0000 H'040000C2 (H'A40000C2)* 16
Transmit data assign register SITDAR R/W H'0000 H'040000C4 (H'A40000C4)* 16
Receive data assign register SIRDAR R/W H'0000 H'040000C6 (H'A40000C6)* 16
Control data assign register SICDAR R/W H'0000 H'040000C8 (H'A40000C8)* 16
Serial control register
SICTR R/W H'0000 H'040000CC (H'A40000CC)* 16
FIFO control register
SIFCTR R/W H'1000 H'040000D0 (H'A40000D0)* 16
Status register
SISTR R/W H'0000 H'040000D4 (H'A40000D4)* 16
Interruption enabling register SIIER R/W H'0000 H'040000D6 (H'A40000D6)* 16
Transmit data register
SITDR W
H'0000 H'040000E0 (H'A40000E0)* 32
Receive data register
SIRDR R
H'0000 H'040000E4 (H'A40000E4)* 32
Transmit control register
SITCR R/W H'0000 H'040000E8 (H'A40000E8)* 32
Receive control register
SIRCR R
H'0000 H'040000EC (H'A40000EC)* 32
Note: * Use the address surrounded by parenthesis when the address translation process by MMU
is not applied. Refer to section 20.3.5, Control Data Interface for more details of the control
data.
Rev. 5.00 Dec 12, 2005 page 607 of 1034
REJ09B0254-0500