SH7727 Datasheet, PDF (892/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
25.5 Usage Notes
Note the following points when using the LCDC.
The following steps should be performed to prohibit access to the system memory used for LCDC
module display (synchronous DRAM in area 3).
(1) Confirm that bits LPS1 and LPS0 in the LDPMMR register are set to 1.
(2) Clear the DON bit in LDCNTR to 0 (display off mode).
(3) Confirm that bits LPS1 and LPS0 in LDPMMR are cleared to 0.
(4) Wait the display duration of one frame.
The above steps to prohibit access are necessary before entering standby mode or using the LCDC
module’s standby function.
Rev. 5.00 Dec 12, 2005 page 820 of 1034
REJ09B0254-0500