SH7727 Datasheet, PDF (515/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 15 Timer (TMU)
Section 15 Timer (TMU)
15.1 Overview
This LSI has an on-chip 32-bit timer unit (TMU) comprised of three 32-bit timer channels
(channels 0 to 2).
15.1.1 Features
The TMU has the following features:
• Auto-reload 32-bit down-counters for each channel
• Auto-reload 32-bit constant registers and 32-bit down counters that can be read or written to at
any time for each channel
• Interrupt request generation at the counter underflow:
Interrupt requests can be generated when the 32-bit down counter underflows (H'00000000 →
H'FFFFFFFF) in each channel.
• Selection of six counter input clocks for each channel:
On-chip RTC output clock (16 kHz), Pφ/4, Pφ/16, Pφ/64, and Pφ/256
• All channels can operate when the SH7727 is in standby mode:
When the RTC output clock is used as the counter input clock, the count operation is normally
performed in standby mode.
• Synchronized read:
TCNT is a 32-bit register that is successively modified. Since the internal bus for the SH7727
on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the
upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read value
caused by this time lag, a synchronization circuit is built in the TCNT so that the entire 32-bit
data in the TCNT can be read at once.
• The maximum 2 MHz operating frequency for the 32-bit counter in each channel:
Operate the SH7727 so that the clock input to each channel timer counter does not exceed the
maximum operating frequency, by dividing the external clock and peripheral clock (Pφ) with
the prescaler.
Rev. 5.00 Dec 12, 2005 page 443 of 1034
REJ09B0254-0500