SH7727 Datasheet, PDF (313/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Power-Down Modes and Software Reset
9.2.4 Module Software Reset Register (SRSTR)
The Software Reset Register (SRSTR) is an 8-bit readable/writable register that controls module
reset operation equivalent to power-on reset. SRSTR is initialized to H'00 by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
SIOFR
—
AFECR USBFR USBHR LBSCR LCDCR PCCR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R/W R/W R/W R/W R/W R/W
Bit 7— SIOF Reset (SIOFR): When the SIOF bit is set to 1, the serial I/O (SIOF) is reset. 0
should be written after writing 1.
Bit 7: SIOFR
0
1
Description
Not reset SIOF
Resets SIOF
(Initial value)
Bit 6—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 5— AFEIF Reset (AFECR): When the AFEC bit is set to 1, the AFE interface (AFEIF) is
reset. 0 should be written after writing 1.
Bit 5: AFECR
0
1
Description
Not reset AFEIF
Resets AFEIF
(Initial value)
Bit 4— USBF Reset (USBFR): When the USBF bit is set to 1, the SUB function module (USBF)
is reset. 0 should be written after writing 1.
Bit 4: USBFR
0
1
Description
Not reset USBF
Resets USBF
(Initial value)
Rev. 5.00 Dec 12, 2005 page 241 of 1034
REJ09B0254-0500