SH7727 Datasheet, PDF (372/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states
inserted into physical space area 6. Also specify the burst pitch for burst transfer.
Bit 15: Bit 14:
A6W2 A6W1
0
0
1
1
0
1
Bit 13:
A6W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Disable
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
(Initial value)
Enable
Bits 12 to 10—Area 5 Wait Control (A5W2, A5W1, A5W0): Specify the number of wait states
inserted into physical space area 5. Also specify the burst pitch for burst transfer.
Bit 12:
A5W2
0
1
Bit 11:
A5W1
0
1
0
1
Bit 10:
A5W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Disable
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
(Initial value)
Enable
Rev. 5.00 Dec 12, 2005 page 300 of 1034
REJ09B0254-0500