SH7727 Datasheet, PDF (127/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Table 2.14 CPU Instruction Formats
Instruction Format
0 type
15
xxxx xxxx xxxx
n type
15
xxxx nnnn xxxx
m type
15
xxxx mmmm xxxx
0
xxxx
0
xxxx
0
xxxx
Source
Operand
—
Destination
Operand
—
Sample Instruction
NOP
—
nnnn: register
MOVT Rn
direct
Control register or nnnn: register
system register direct
STS MACH,Rn
Control register or nnnn: pre-
STC.L SR,@-Rn
system register decrement register
indirect
mmmm: register
direct
Control register or LDC
system register
Rm,SR
mmmm: post-
Control register or LDC.L @Rm+,SR
increment register system register
indirect
mmmm: register —
indirect
JMP @Rm
PC-relative using —
Rm
BRAF Rm
Rev. 5.00 Dec 12, 2005 page 55 of 1034
REJ09B0254-0500