SH7727 Datasheet, PDF (734/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
(2) AFEIF Control Register 2 (ACTR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
DPST PPS RCEN
—
RLYC
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R/W
R/W
R
R/W
Bits 15 to 5, and 1—Reserved
Bit 4—Dial Pulse Start (DPST): Start bit of dial pulse. Dial number within the DPNQ register is
output to AFE_RLYCNT as specified by PPS, MRCR and MPCR. After all dial number is output ,
DPE interrupt is generated to modify the DPST bit to 0. See section 21.3.3, DAA Interface for
more detail about dial pulse output sequence. Take care that AFE_RLYCNT must be “H” to
enable dial pulse generating circuit
Bit 3—Dial Pulse Duration Set (PPS)
Bit 3: PPS
0
1
Description
10PPS
20PPS
(Initial value)
Bit 2—Ringing Counter Enable (RCEN)
Bit 2: RCEN
Description
0
Stop Ringing Counter
1
Start Ringing Counter
Note: See section 21.3.3, DAA Interface for more detail about how to count.
(Initial value)
Rev. 5.00 Dec 12, 2005 page 662 of 1034
REJ09B0254-0500