SH7727 Datasheet, PDF (808/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 24 USB HOST Module
Register: HcInterruptStatus
Bits
Reset
R/W
4
0b
R/W
3
0b
R/W
2
0b
R/W
1
0b
R/W
0
0b
R/W
Offset: 0C–0F
Description
UnrecoverableError (UE)
This bit is set when the host controller detects a system error
that is not related to USB. HCD clears this bit after the host
controler is reset.
0: System error has not generated yet. (initial value)
1: System error is detected.
ResumeDetected (RD)
This bit is set when the host controller detects that a device of
USB issues a resume signal. This bit is not set when HCD sets
UsbResume state.
0: The resume signal is not detected. (initial value)
1: The resume signal is detected.
StartofFrame (SF)
This bit is set by the host controller when each frame starts and
after the HccaFrameNumber is updated. The host controller
simultaneously generates the SOF token.
0: Each frame has not initiated or HccaFrame Number is not
updated (initial value)
1: Initiation of each frame and updating of HccaFrameNumber
WritebackDoneHead (WDH)
This bit is set immediately after the host controller has written
HcDoneHead to HccaDoneHead. HccaDoneHead is not
updated until this bit is cleared. HCD should clear this bit only
after the content of HccaDoneHead has been stored.
0: When cleared after set to 1. (initial value)
1: When HcDoneHead is written to HccaDonehead.
SchedulingOverrun (SO)
This bit is set when the USB schedule has overrun after
HccaFrameNumber has updated. SchedulingOverrun also
increments the SchedulingOverrunCount bit in
HcCommandStatus.
0: The USB schedule has not overrun. (initial value)
1: The USB schedule has overrun.
Rev. 5.00 Dec 12, 2005 page 736 of 1034
REJ09B0254-0500