SH7727 Datasheet, PDF (200/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
3.7 Usage Notes
1. Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction,
LDC @Rm+, SR instruction, and RTE instruction) and the following instruction, or the
LDTLB instruction, should be used with the TLB disabled or in a fixed physical address
space (the P1 or P2 space).
2. The value of the RC bit in MMUCR may be set abnormally if all of the following conditions
are met:
(1) MMU is on (AT is set to 1 in MMUCR).
(2) Identical entries in the TLB address array reference the same VPN using multiple ways.
(3) A TLB related exception occurs.
The VPN is not initialized at power on reset or manual reset. Therefore, identical entries may
access two or more VPNs using the same value. In such cases, certain entries in the TLB
address array may end up as shown below if, for example, they are registered in way 3.
In this case way 0 and way 3 reference the same VPN, thereby satisfying condition (2).
After reset
WAY VPN V
0
12345 0
3
12345 0
After registration to way 3
WAY VPN V
0
12345 0
3
12345 1
The above conditions can also be satisfied by TLB handling in software. For example, the
situation shown below could occur if, after invalidating way 0 (by setting V from 1 to 0) for an
entry in the TLB address array, the entry is registered to way 3. In this case as well, the same
VPN is assigned for both way 0 and way 3, thereby satisfying condition (2) above.
After invalidation of way 0 After registration to way 3
WAY VPN V
WAY VPN V
0
12345 0
0
12345 0
3
11111 0
3
12345 1
Rev. 5.00 Dec 12, 2005 page 128 of 1034
REJ09B0254-0500