SH7727 Datasheet, PDF (263/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
Bit 0—DEI0 Interrupt Request (DEI0R): Indicates whether a DEI0 (DMAC) interrupt request
is generated.
Bit 0: DEI0R
0
1
Description
A DEI0 interrupt request is not generated
A DEI0 interrupt request is generated
(Initial value)
7.3.9 Interrupt Request Register 2 (IRR2)
The IRR2 is an 8-bit read-only register that indicates whether A/D converter, or SCIF interrupt
requests are generated. This register is initialized to H'00 at power-on reset or manual reset, but is
not initialized in standby mode.
Bit: 7
6
5
4
3
2
1
0
—
—
—
ADIR TXI2R BRI2R RXI2R ERI2R
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 4—ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request is
generated.
Bit 4: ADIR
0
1
Description
An ADI interrupt request is not generated
An ADI interrupt request is generated
(Initial value)
Bit 3—TXI2 Interrupt Request (TXI2R): Indicates whether a TXI2 (SCIF) interrupt request is
generated.
Bit 3: TXI2R
0
1
Description
A TXI2 interrupt request is not generated
A TXI2 interrupt request is generated
(Initial value)
Rev. 5.00 Dec 12, 2005 page 191 of 1034
REJ09B0254-0500