SH7727 Datasheet, PDF (282/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
8.2.5 Break Address Mask Register B (BAMRB)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address
specified by BARB. A power-on reset initializes BAMRB to H'00000000.
XYE = 0
XYE = 1
BAMB31 to 16
Mask L(I) AB31 to 16
Mask XAB15 to 1 (XYS = 0)
BAMB15 to 0
Mask L(I) AB15 to 0
Mask YAB15 to 1 (XYS = 1)
Bits 31 to 0:
BAMBn
0
1
Description
Break address BABn of channel B is included in the break condition (Initial value)
Break address BABn of channel B is masked and is not included in the break
condition
n = 31 to 0
Rev. 5.00 Dec 12, 2005 page 210 of 1034
REJ09B0254-0500