SH7727 Datasheet, PDF (697/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
Bit10—Receive Control Data Ready Enable (RCRDYE)
Bit10: RCRDYE
0
1
Description
Disable interrupt of receive control data ready
(Initial value)
Enable interrupt of receive control data ready (control interrupt)
Bit 9—Receive FIFO Full Enable (RFFULE)
Bit 9: RFFULE
0
1
Description
Disable interrupt of receive FIFO full
Enable interrupt of receive FIFO full (control interrupt)
(Initial value)
Bit 8—Receive Data Transfer Request Enable (RDREQE)
Bit 8: RDREQE
0
1
Description
Disable interrupt of receive data transfer request
(Initial value)
Enable interrupt of receive data transfer request (receive interrupt)
Bit 4—Frame Synchronization Error Enable (FSERRE)
Bit 4: FSERRE
0
1
Description
Disable interrupt of frame synchronization error
Enable interrupt of frame synchronized error (error interrupt)
(Initial value)
Bit 3—Transmit FIFO Over Run Enable (TFOVRE)
Bit 3: TFOVRE
0
1
Description
Disable interrupt of transmit FIFO over run
Enable interrupt of transmit FIFO over run (error interrupt)
(Initial value)
Bit 2—Transmit FIFO Under Run Enable (TFUDRE)
Bit 2: TFUDRE
0
1
Description
Disable interrupt of transmit FIFO under run
Enable interrupt of transmit FIFO under run (error interrupt)
(Initial value)
Rev. 5.00 Dec 12, 2005 page 625 of 1034
REJ09B0254-0500