SH7727 Datasheet, PDF (721/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
(3) A Case of 16 bits Monaural (No.1)
Sync pulse method, falling edge sampling, transmit data and receive data are assigned to slot No.
0, frame length is 64 bits.
1 frame
SCK_SIO
SIOFSYN
TXD_SIO
RXD_SIO
Lch. DATA
Slot No.0
1 bit delay
Slot No.1
Slot No.2
Slot No.3
Setting: TRMD = 00 or 10, REDG = 0,
FL=1101 (frame length 64 bits)
TDLE = 1,
TDLA3 to TDLA0 = 0000, TDRE = 0, TDRA3 to TDRA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000,
CD0E = 0,
CD0A3 to CD0A0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 20.15 Transmit or Receive Timing (16 bits monaural—1)
(4) A Case of 16 bits Stereo (No.1)
L/R method, rising edge sampling and Lch. data are assigned to slot No. 0, Rch.data is assigned to
slot No. 1, and frame length is 32 bits.
1 frame
SCK_SIO
SIOFSYN
TXD_SIO
RXD_SIO
Lch. DATA
Slot No.0
No delay
Rch. DATA
Slot No.1
Setting: TRMD = 11,
TDLE = 1,
RDLE = 1,
CD0E = 0,
REDG = 1,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0= 0000,
CD0A3 to CD0A0 = 0000,
FL = 1100 (flame length 32 bits),
TDRE = 1, TDRA3 to TDRA0 = 0001,
RDRE = 1, RDRA3 to RDRA0 = 0001,
CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 20.16 Transmit or Receive Timing (16 bits stereo—1)
Rev. 5.00 Dec 12, 2005 page 649 of 1034
REJ09B0254-0500