SH7727 Datasheet, PDF (171/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Process 1
Physical
memory
Section 3 Memory Management Unit (MMU)
Process 1
Physical
memory
Process 1
Virtual
memory
MMU
Physical
memory
(1)
Process 1
Physical
memory
Process 2
(2)
Process 1
Process 2
Virtual
memory
MMU
Physical
memory
Process 3
Process 3
(3)
(4)
Figure 3.1 MMU Functions
3.1.3 SH7727 MMU
Logical Address Space: The SH7727 uses 32-bit logical addresses to access a 4-Gbyte logical
address space that is divided into several areas. Address space mapping is shown in figure 3.2.
In the privileged mode, there are five areas, P0 to P4.
The P0 and P3 areas are mapped onto physical address space in page units, in accordance with
address translation table information. Write-back or write-through can be selected for write access
by means of a CCR setting.
Mapping of the P1 area is fixed in physical address space (H'00000000 to H'1FFFFFFF). In the
P1 area, setting a logical address MSB (bit 31) to 0 generates the corresponding physical address.
P1 area accesses can be cached, and the cache control register (CCR) is set to indicate whether to
cache or not. Write-back or write-through mode can be selected.
Rev. 5.00 Dec 12, 2005 page 99 of 1034
REJ09B0254-0500