SH7727 Datasheet, PDF (476/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Figure 14.4 shows how the priority order changes when transfer requests for channel 0 and
channel 3 are generated simultaneously and a transfer request for channel 1 is requested during the
channel 0 transfer. The DMAC operates as follows:
1. Transfer requests are generated simultaneously for channels 0 and 3.
2. Channel 0 has the higher priority, so the channel 0 transfer begins first (channel 3 waits for
transfer).
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
waiting)
4. When the channel 0 transfer ends, channel 0 has the lowest priority.
5. At this time, channel 1 has the higher priority than channel 3, so the channel 1 transfer begins
(channel 3 waits for transfer).
6. When the channel 1 transfer ends, channel 1 has the lowest priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority order so that
channel 3 has the lowest priority.
Transfer request Waiting channel(s) DMAC operation
Channel priority
(1) Channels 0 and 3
(3) Channel 1
(2) Channel 0 transfer
3
start
1,3 ^{(4) Channel 0 transfer}
ends
0>1>2>3
Priority order
changes
1>2>3>0
(5) Channel 1 transfer
starts
Priority order
3 (6) Channel 1 transfer ^changes
2>3>0>1
ends
(7) Channel 3 transfer
starts
None
(8) Channel 3 transfer
ends
Priority order
changes
0>1>2>3
Figure 14.4 Channel Priority Order in Round-Robin Mode
Rev. 5.00 Dec 12, 2005 page 404 of 1034
REJ09B0254-0500