SH7727 Datasheet, PDF (934/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 28 A/D Converter
28.2.2 A/D Control/Status Register (ADCSR)
Bit: 7
6
ADF ADIE
Initial value: 0
0
R/W: R/(W)* R/W
Note: * Write 0 to clear the flag.
5
ADST
0
R/W
4
MULTI
0
R/W
3
CKS
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
ADCSR is an 8-bit read/write register that controls the A/D converter and indicates the status.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7: ADF
0
1
Description
[Clear condition]
(Initial value)
(1) Cleared by reading ADF while ADF = 1, then writing 0 in ADF
(2) Cleared when DMAC is activated by ADI interrupt and ADDR is read
[Set conditions]
Single mode: A/D conversion ends
Multi mode and scan mode: A/D conversion ends in all selected channels
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6: ADIE
0
1
Description
A/D end interrupt request (ADI) is disabled
A/D end interrupt request (ADI) is enabled
(Initial value)
Rev. 5.00 Dec 12, 2005 page 862 of 1034
REJ09B0254-0500