SH7727 Datasheet, PDF (648/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.7 Serial Status Register 2 (SCSSR2)
Serial status register 2 (SCSSR2) is a 16-bit register. The upper 8 bits indicate the number of
receive errors in the data of receive FIFO data register 2, and the lower 8 bits indicate SCIF
operating state.
The CPU can always read and write the SCSSR2, but cannot write 1 in the status flags (ER,
TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been
read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. The
SCSSR2 is initialized to H'0060 by a reset or in standby and module standby modes.
Lower 8 bits: 7
6
5
4
3
ER TEND TDFE BRK FER
Initial value: 0
1
1
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)*
R
Note: * The only value that can be written is 0 to clear the flag.
2
PER
0
R
1
RDF
0
R/(W)*
0
DR
0
R/(W)*
Bit 7—Receive Error (ER): Indicates that a parity error has occurred when received data
includes a framing error or a parity.
Bit 7: ER
Description
0
Receive is in progress, or receive is normally completed.^*1
(Initial value)
ER is cleared to 0 when the chip is reset or enters standby mode, or when 0 is
written after 1 is read from ER.
1
A framing error or a parity error has occurred.
ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit
of the received data is 1 at the end of one-data receive^*2, or when the total
number of 1's in the received data and in the parity bit does not match the
even/odd parity specification specified by the O/E bit of the SCSMR2.
Notes: 1. Clearing the RE bit to 0 in SCSCR2 does not affect the ER bit, which retains its
previous value. Even if a receive error occurs, the received data is transferred to
SCFRDR2 and the receive operation is continued. Whether or not the data read from
SCFRDR2 includes a receive error can be detected by the FER and PER bits of
SCSSR2.
2. In the stop mode, only the first stop bit is checked; the second stop bit is not checked.
Rev. 5.00 Dec 12, 2005 page 576 of 1034
REJ09B0254-0500