SH7727 Datasheet, PDF (717/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
(5) Transmit or Receive Reset
SIOF can reset independently the transmit and receive portions by setting 1 in the following bits.
• Transmit reset: (TXRST bit of SICTR register)
• Receive reset: (RXRST bit of SICTR register)
Table 20.11 shows the initialized contents by transmit or receive reset.
Table 20.11 Transmit or Receive Reset
Reset Type
Transmit reset
Receive reset
Initialized Register or Bits
SITDR register
Transmit FIFO write pointer
Transmit FIFO read pointer
TCRDY, TFEMP, and TDREQ bits in SISTR register
TXE bit in SICTR register
SIRDR register
Receive FIF0 write pointer
Receive FIF0 read pointer
RCRDY, RFFUL, and RDREQ bits in SISTR register
RXE bit in SICTR register
(6) Module Stop
SIOF stops transmit or receive operation with holding the contents of all registers at module stop.
Issue the transmit or receive reset, when the transmit or receive operation is not executed directly
after the module stop.
Rev. 5.00 Dec 12, 2005 page 645 of 1034
REJ09B0254-0500